The present invention relates generally to an interface for embedded DRAM.
In most applications, the DRAM memory is intended to support the operation of one or more logic devices (e.g., microprocessors). In conventional DRAM applications, a dedicated chip(s) containing the DRAM memory was typically employed separate from the chip containing the microprocessor(s) or other logic devices. The data/control transmission between the DRAM and the logic device would typically be managed through a bus architecture on the circuit board containing the various chips. In such conventional configurations, the selection of DRAM architecture and interface was largely predetermined by the DRAM manufacturer and/or industry standards for the particular type of DRAM memory.
Where logic device manufacturers (e.g., ASICs manufacturers) had desired memory on the logic chip, this was generally accomplished using static random access memory (SRAM). Unfortunately, SRAM consumes a significant amount of chip area relative to the memory capacity provided (i.e., a single SRAM data cell usually requires on the order of six transistors). Thus, more recently, logic device manufacturers have moved toward the use of eDRAM for on-chip memory in order to conserve chip area and/or increase performance through more on-chip memory capacity. The motivation to replace SRAM implementations with eDRAM places additional pressure on macro performance and random cycle time.
The desire to embed DRAM into logic chips has resulted in the need for development of DRAM macro designs which are amenable to logic design environments. The logic or ASIC environment presents many difficult challenges that DRAMs have historically been sensitive to, such as wide voltage and temperature ranges and uncertainties in surrounding noise conditions. There is a need for DRAM macro designs having performance characteristics which can be varied by the logic designer without significant restructuring of the DRAM macro. There is also a desire for DRAM macro designs having improved bus utilization and speed.
The invention provides a synchronous multibank interface on a growable embedded DRAM. The flexible multibank interface of the invention can be grown without redesign and without change of appearance/behavior to the customer. The interface is preferably characterized by the presence of bank select inputs (pins) which permit selection of one or more banks of the macro. The banks preferably each have respective support circuitry including row decode circuitry and respective limited repair redundancy. The interface of the invention has advantages over typical synchronous DRAM interfaces in that operations to each bank are independent. Also, activation and pre-charge operations can both be completely hidden during reads and writes. The interface of the invention may be used to support multiple bank configurations with any number of banks (i.e., one or more banks).
In one aspect, the invention encompasses a multibank DRAM macro comprising:
(a) a plurality of DRAM memory banks, each bank respectively comprising:
(i) an array of DRAM memory cells,
(ii) bitlines and wordlines, respectively defining columns and rows of the array, and
(iii) a row address decoder circuit,
(iv) a column address decoder circuit,
(v) spare rows and columns for redundancy,
(b) a bank select input for each respective bank, each bank input controlling operation of its respective bank, and
(c) a data path receiver/driver shared by at least two banks.
The macro preferably further includes a master select input capable of latching all the bank select inputs and row address inputs. The macro further includes a shared data path for all banks.
In another aspect, the invention encompasses a methods for operating the eDRAM macro of the invention.
These and other aspects of the invention are described in further detail below.